Dovado: an Open-Source Design Space Exploration Framework Why

Traditional hardware development exploits description languages such as VHDL and (System)Verilog to produce highly parametrizable RTL designs. Different parameter values yield different utilization-frequency trade-offs, and hand-tuning is not feasible with a non-trivial amount of parameters. Generally, the Computer-Aided Design (CAD) literature proposes approaches that mainly tackle automatic exploration without combining a design automation feature.

What

Dovado is an open-source CAD tool for design space exploration (DSE) tailored for FPGA-based designs. Starting from VHDL/(System)Verilog, Dovado exploits Vivado and supports the hardware developer for an exact exploration of a given set of parameters or a DSE where it returns the non-dominated set of configuration points.

How

Dovado is implemented in pure Python and employs ANTLR to parse VHDL/(System)Verilog projects. On top of this, several TCL scripts have been developed to automate synthesis and implementation with Vivado. Finally, VHDL/(System)Verilog boxes have been designed to avoid pin overflow when exploring non-top modules.